MAXEDA Webinar - 如何使用MaxPlace解決顯示器驅動晶片繞線與時序問題


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[Webinar] How to use MaxPlace to improve Timing and Congestion of Display Driver IC

Here we accelerate your physical design process

Wirelength minimization, Routing space allocation and Blockage insertion

在狹長型的Display Driver IC上，如何解決實體設計上的 Timing 以及 Congestion的問題，一直是工程師的極大挑戰，透過這次研討會，Maxeda會介紹在進入實體設計階段時，如何利用MaxPlace所提供的獨特功能，來快速及有效的解決相關問題，並達到各項技術指標的要求。

Schedule: 02/24 (Thursday) 2:00 ~ 2:30pm

Agenda:
•Maxeda Highlight
•Product Overview
•Display Driver IC Challenges for Congestion/Timing
•MaxPlace Solutions for Display Driver IC
•Our next step - ML
•Q&A

Product and Service

MaxFlow

Dataflow Analyzer and Viewer

MaxPlace

Floorplan Exploration System and Mixed-size Placer

Customize

Customized toolbox, and APR Flow integration

Maxeda Technology is an EDA (electronic design automation) company providing innovative products and solutions in the physical design process to support engineers to overcome the design challenges when IC complexity is increasing together with macro quantities.

Our products include MaxFlow for dataflow analysis viewer and MaxPlace for floorplan exploration system to support customers to achieve the goal of better PPA and shorter TAT.

Maxeda Tech

14F-6, No. 27, Guanxin Rd., HsinChu
Taiwan

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TEL: +886-3621-4888

sales@maxeda.tech

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